/*
 * @(#)XfvhdlRulesMemFile.java        3.0                     2004/09/14
 *
 * This file is part of Xfuzzy 3.0, a design environment for fuzzy logic
 * based systems.
 *
 * (c) 2000 IMSE-CNM. The authors may be contacted by the email address:
 *                    xfuzzy-team@imse.cnm.es
 *
 * Xfuzzy is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
 * Xfuzzy is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */

package xfuzzy.xfvhdl;

import xfuzzy.lang.*;
import java.io.*;

/**
* Clase que genera el fichero de la memoria de reglas RulesMem.vhdl.
* @author Jos� Mar�a �vila Maireles, <b>e-mail</b>: josavimai@alum.us.es
* @version 3.0
*/
public class XfvhdlRulesMemFile implements XfvhdlIRulesMem {

   //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
   //			  M�TO_DOS P�BLICOS DE LA CLASE				       
   //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//

   /**
   * M�todo que crea la cadena que ser� escrita en fichero RulesMem.vhdl.
   * @return Devuelve la cadena que ser� escrita en fichero RulesMem.vhdl.
   */
   public String createRulesMemSource(Specification spec)
      throws IOException {

      XfvhdlRulesMemData contenido =
         new XfvhdlRulesMemData(
            XfvhdlProperties.dir_regl,
            XfvhdlProperties.N,
            XfvhdlProperties.K,
            spec);

      XfvhdlHeadFile head =
         new XfvhdlHeadFile(
            XfvhdlProperties.fileDir,
            XfvhdlProperties.outputFile + "RulesMem.vhdl",
            XfvhdlProperties.ficheroXFL);

      String code = head.getHead();

      code
         += "\n--***********************************************************************--\n"
         + "--                                                                       --\n"
         + "--   DESCRIPTION: This file contains the VHDL description for the        --\n"
         + "--                rules memory of the fuzzy controller.                  --\n"
         + "--                                                                       --\n"
         + "---------------------------------------------------------------------------\n"
         + "--                                                                       --\n"
         + "--   AUTHOR:      Jose Maria Avila Maireles                              --\n"
         + "--                                                                       --\n"
         + "--   VERSION:     Xfvhdl  ver0.1                          January 2004   --\n"
         + "--                                                                       --\n"
         + "--***********************************************************************--\n"
         + "\n"
         + "\n"
         + "library IEEE;\n"
         + "use IEEE.std_logic_1164.all;\n"
         + "use IEEE.std_logic_unsigned.all;\n"
         + "\n"
         + "use WORK.Constants.all;\n"
         + "\n"
         + "\n"
         + "---------------------------------------------------------------------------\n"
         + "--                           Entity description                          --\n"
         + "---------------------------------------------------------------------------\n"
         + "\n"
         + "entity RulesMem is\n"
         + "\n"
         + "\tport(\taddr\t: in std_logic_vector(dir_regl downto 1);" +         	"\t\t-- Address bus\n"
         + "\t\tme\t: in std_logic;\t\t\t\t\t\t-- Memory enable\n"
         + "\n"
         + "\t\tdo\t: out std_logic_vector(w_reglas downto 1));" +         	"\t-- Data bus\n"
         + "\n"
         + "end RulesMem;\n"
         + "\n"
         + "\n"
         + "---------------------------------------------------------------------------\n"
         + "--                       Architecture description                        --\n"
         + "---------------------------------------------------------------------------\n"
         + "\n"
         + "architecture FPGA of RulesMem is\n"
         + "\n"
         + "\tsignal data: std_logic_vector(w_reglas downto 1);\n"
         + "\n"
         + "begin\n"
         + "\n"
         + "\tProceso_Lectura: process(me, addr)\n"
         + "\t\tbegin\n"
         + "\n"
         + "\t\t\tif (me = '1' and not me'stable) then\n"
         + "\t\t\t\tcase addr is\n";

      for (int i = 0; i < contenido.getLength(); i++) {
         if (contenido.isActive(i)
            && XfvhdlProperties.calculateWeights == false) {
            code += "\t\t\t\t\twhen \""
               + contenido.getLine(i)
               + "\" => data <= \""
               + contenido.getValue(i)
               + "\";\n";
         } else if (
            contenido.isActive(i)
               && XfvhdlProperties.calculateWeights == true) {
            code += "\t\t\t\t\twhen \""
               + contenido.getLine(i)
               + "\" => data <= \""
               + contenido.getValue(i)
               + ""
               + contenido.getWeight(i)
               + "\";\n";
         }
      }

      XfvhdlBinaryDecimal converter = new XfvhdlBinaryDecimal();

      code += "\t\t\t\t\twhen others => data <= \"" +
      /*converter.toBinary(XFvhdlProperties.DONT_CARE,
       * XFvhdlProperties.w_reglas)*/
      converter.toHyphen(XfvhdlProperties.w_reglas) + "\";\n";
      code += "\t\t\t\tend case;\n"
         + "\t\t\tend if;\n"
         + "\n"
         + "\t\tend process Proceso_Lectura;\n\n"
         + "\t\tdo <= data;\n\n"
         + "\tend FPGA;";

      return code;
   }

} // Fin de la clase
